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Advanced Silicon Devices:
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Metal-oxide-semiconductor field-effect transistors, silicon workhorses at the heart of information technology, have been scaling to ever smaller dimensions for higher performance integrated circuits for over a quarter century. But there are limits to scaling. For example, transistor leakage currents from quantum mechanical tunneling have complicated scaling for the last few years and will impose further, unavoidable constraints going forward. This course focusses on the physical mechanisms that constrain scaling and the technological approaches undertaken to avoid these constraints. The mechanisms include tunneling leakages and electrostatic control of the channel charge. The innovations developed to mitigate these mechanisms include high-K gate dielectrics, metal gates, and strained silicon. Finally, after discussing the limits to scaled silicon MOSFETs, some alternative replacement MOSFET geometries and alternative devices will be briefly reviewed. |
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Instructor Mark Miller (mark.miller@utah.edu) Office: 314 EMRO. Phone: 587-7718 Office hours: W, Th 1:30 – 2:30 |
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Text: Fundamentals of Modern VLSI Devices, by Yuan Taur and Tak H. Ning, Cambridge University Press, 1998. ISBN: 0521559596 Papers and other literature at: ScaledMOSFETs/Literature/index.html Lectures Tuesday and Thursday, 12:25 - 1:45, WBB 206 |
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Homework Homework will be assigned each week, and is due in class the following week. Exams: There will be a midterm exam and a comprehensive final exam. Report: There will be a written report and accompanying presentation on a topic connected to the scaled MOSFETs of this class. Grading: The course grade will be distributed as: 15% homework, 25% report and presentation, 25% midterm, and 35% for the final exam. |